Digital Lab (PCCSL308) Syllabus

Part A (mandatory, breadboard/circuit-simulation software): study of basic digital ICs and verification of Boolean theorems using logic gates; realizing basic logic gates and analyzing waveforms; realizing a Boolean function using basic gates and verifying against the truth table; familiarization of Verilog HDL — gate level, behavioural, structural and dataflow modelling of basic gates; realization of SOP/POS expressions using NAND-only and NOR-only gates; modelling a Boolean function (SOP and POS) in Verilog using continuous assignment (logical/conditional operators) and gate-level primitives.

Part B (circuit simulation software): combinational logic circuits for code converters, half/full adder, half/full subtractor, multiplexer, demultiplexer, encoder, decoder; combinational circuits using MSI devices — 4-bit adder/subtractor (IC 7483), parity generator/checker (IC 74180), magnitude comparator (IC 7485), Boolean function using MUX IC; D flip-flop and JK flip-flop study using ICs; shift registers (SISO, SIPO, PISO, PIPO) using D flip-flops; asynchronous and synchronous counters (up, down, up-down with mode control, mod-N, sequence generator).

Part C (Verilog HDL, using Icarus Verilog / EDAplayground or similar): modelling a 4:1 MUX, 1:4 DEMUX, 4-to-2 encoder, 2-to-4 decoder and a 7-segment display decoder using continuous assignment; behavioural model for a D flip-flop; behavioural model for a synchronous counter; behavioural model for a finite state machine (serial bit sequence detector). Each experiment requires writing the Verilog code, simulating with a test bench, and synthesizing/verifying the design's waveforms.