Digital Electronics and Logic Design (GAEST305) Syllabus

Introduction to Digital Systems: digital abstraction, number systems — binary, hexadecimal, grouping bits, base conversion; binary arithmetic — addition and subtraction, unsigned and signed numbers; fixed-point and floating-point number systems. Basic Gates: operation of a logic circuit, buffer, gates (inverter, AND, OR, NOR, NAND, XOR, XNOR), digital circuit operation (logic levels, DC specifications, noise margins, power supplies), driving loads. Verilog (Part 1): HDL abstraction, modern digital design flow, Verilog constructs — data types, the module, Verilog operators.

Combinational Logic Design: Boolean algebra (operations, axioms, theorems), combinational logic analysis (canonical SOP and POS, minterm and maxterm equivalence), logic minimization (algebraic minimization, K-map minimization, don't cares, code converters). Modeling concurrent functionality in Verilog: continuous assignment with logical operators, conditional operators, and delay.

MSI Logic and Digital Building Blocks: MSI logic — decoders (one-hot decoder, 7-segment display decoder), encoders, multiplexers, demultiplexers; digital building blocks — arithmetic circuits (half adder, full adder, half subtractor, full subtractor), comparators. Structural design and hierarchy: lower-level module instantiation, gate-level primitives, user-defined primitives, adding delay to primitives.

Sequential Logic Design: latches and flip-flops — SR latch, SR latch with enable, JK flip-flop, D flip-flop, register enabled flip-flop, resettable flip-flop; sequential logic timing considerations; common circuits based on sequential storage devices — toggle flop clock divider, asynchronous ripple counter, shift register. Finite State Machines: logic synthesis for an FSM, FSM design process and design examples, synchronous sequential circuits (counters). Verilog (Part 2): procedural assignment, conditional programming constructs, test benches, modeling a D flip-flop and an FSM in Verilog.